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  Huawei Zurich Research Center

  • Principal Researcher · Team & Technical LeadMay 2025 – present

    Lead a research team at the intersection of storage and AI: storage systems that accelerate LLM inference and agentic-AI workloads, alongside CXL-based memory systems for modern data centers.

    KV-cache systems for LLM inference. Persist and reuse KV caches beyond exact prefix matches via selective recomputation of a small token fraction; offload caches across GPU memory, DRAM, and NVMe, managing bandwidth to sustain cache loading under concurrent inference — prototyped on vLLM, SGLang, and LMCache.

    RAG serving. Speculative decoding that drafts tokens from the retrieval datastore and verifies them in parallel on the target model, removing the separate draft model; approximate caching of retrievals across similar queries.

    Systems for agentic AI. New system interfaces and file systems for AI agents, including offloading agents’ data operations into storage (in-storage processing).

  • Senior ResearcherAug 2023 – May 2025

    Distributed caching over memory fabrics. Designed an OS-level distributed page cache for CXL 3.0 shared memory that keeps a single DRAM copy of each file page across nodes while preserving POSIX semantics — up to 12.4× speedups in multi-host emulation.

    UnifiedBus. Contributed to the specification of UnifiedBus (UB), Huawei’s openly published interconnect for peer-to-peer resource pooling in SuperPoD-scale AI systems.

    In-storage processing. Accelerated approximate-nearest-neighbor vector search inside storage devices to cut data movement for retrieval and vector-database workloads.

    MoE inference offload. Enabled Mixture-of-Experts LLM inference on memory-constrained servers by offloading expert (FFN) weights to fast storage and streaming the experts activated per token.

    Power-efficient storage servers. Co-led an I/O-metric-guided CPU power-management subsystem (DVFS and core power-gating) for all-flash storage servers, improving IOPS per watt on production traces at no performance cost.

    SMT scheduling. Devised symbiosis-aware scheduling that co-locates threads with complementary resource profiles on SMT cores, raising throughput without hardware changes.

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  Chief Architect, Advanced Technologies

  UniFabrix

  2022 – 2023

  CXL memory pooling. Architected dynamic borrowing and lending of memory across hosts over CXL, built on Linux memory hot-plug; hardware/software co-design and OS support for disaggregated memory.

  Performance frameworks. Built frameworks that let applications consume pooled memory without performance loss — and with gains where the pool’s added bandwidth is exploited.

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  Visiting Scholar

  Imperial College London

  2022

  Designed a memory-virtualization mechanism that lets VMs manage flat guest-virtual-to-host-physical page tables, with inter-VM isolation enforced through per-VM physical-memory tagging repurposed from confidential-computing hardware; with Prof. Peter Pietzuch and Prof. Lluís Vilanova. Prototyped in Linux/KVM/QEMU on x86-64: near-native paging — up to 2.4× faster than nested paging (Intel EPT).

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  Ph.D. & Lecturer, Electrical & Computer Engineering

  Technion — Israel Institute of Technology

  2017 – 2022

  Ph.D. thesis “Memory Management for Emerging Memory Technologies in Future Data-Centers,” advised by Prof. Mark Silberstein.

  Disaggregated memory & storage. A Linux memory-tiering subsystem for high-latency far memory (HotBox, ISMM ’22) and a redesign of the Linux swap subsystem for ZNS SSDs (ZNSwap, USENIX ATC ’22 / ACM TOS ’23).

  Virtualization. Near-native memory virtualization via guest-managed flat page tables with CPU physical-memory tagging (TPT, USENIX ATC ’23).

  Teaching. Lecturer and TA-in-charge for “Structure of Operating Systems”; mentored graduate students, including the nested-virtualization work that became HyperTurtle (Best Paper, USENIX ATC ’25).

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  Software Architect, Innovation Team

  Toga Networks — a Huawei Company

  2019 – 2021

  Consultant (2020–2021). Architected memory management that removes memory-pinning for next-generation RDMA NICs: NIC-side on-the-fly address translation with page-fault handling and requester/responder memory-status signaling — three patent families (US and EP patents granted). Also designed efficient intra-host data movement for UCX.

  Intern (2019). Linux kernel memory-management development for HPC systems.

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  Software Engineer, Runtime Team

  LogicBlox

  2016

  Implemented and optimized vectorized (SIMD) query execution in the LogicBlox 4 runtime — a commercial Datalog (LogiQL) database engine — and investigated GPU offload for accelerating query evaluation.

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  Co-Op Engineer, Innovation Team

  AMD

  2015

  Prototyped OS support for transparent peer-to-peer DMA between NVMe SSDs and GPUs with standard POSIX file semantics, removing the CPU from the data path — paving the way for later GPU-direct storage technologies such as NVIDIA GPUDirect Storage (GDS).

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  M.Sc. & Teaching Assistant, Electrical & Computer Engineering

  Technion — Israel Institute of Technology

  2015 – 2017

  Thesis “High-Performance Disk I/O on GPUs”: OS-integrated peer-to-peer DMA between NVMe SSDs and GPUs behind standard POSIX file I/O (SPIN, USENIX ATC ’17). TA-in-charge for “Structure of Operating Systems.” Cum Laude (thesis 95%, courses 96.7%).

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  B.Sc., Electrical & Computer Engineering

  Technion — Israel Institute of Technology

  2011 – 2015

  Specialization in Computers (hardware & software) and Networks. Cum Laude (average 90.2%).

Awards & honors